1. Technical Field
The present invention relates to a substrate and a manufacturing method of the same, and a semiconductor device and a manufacturing method of the same.
2. Related Art
Semiconductor packages are classified broadly into a peripheral type package in which external terminals are arranged at the periphery of the package and an area type package in which external terminals are disposed at the under surface of the package. Packages typified by DIP (dual inline package), SOP (small outline package), and QFP (quad flat package) are the peripheral type package, as shown in FIGS. 40A through 40C. As shown in FIG. 40D, the peripheral type package is manufactured such that an integrated circuit (IC) element 210 is mounted on a die pad 201 that is a chip mounting part, an electrode provided on the IC element 210 is connected with a lead 203 of a lead frame by a gold wire, and then the whole except for a part of the peripheral part of the lead 203 is sealed with a resin. A part of the lead 203 inside the resin package is called an internal terminal, and a part outside the resin package is called an external terminal.
Packages typified by BGA (ball grid array) are the area type package, as shown in FIGS. 41A through 42B. The area type package is manufactured such that an IC element 210 is mounted on a substrate 211, the IC element 210 is electrically coupled with the substrate 211 with a gold wire, solder, or a gold bump, and the IC element 210 and the like are sealed with a resin. Packages in which the substrate 211 is connected with the IC element 210 with a gold wire 213 shown in FIGS. 41A and 41B are called a gold wire type BGA as well.
Packages in which the substrate 211 is coupled with the IC element 210 with a bump 223 shown in FIGS. 42A and 42B are called a bump type BGA. Especially in some bump type BGAs, a resin sealing is not conducted, as shown in FIGS. 42A and 42B. As shown in FIGS. 41A through 42B, an external terminal of the area type package is not a lead but an electrode (or, a solder ball) 225 disposed on a back surface of the substrate 211.
In addition, recently, as shown in FIGS. 43A through 43I, a package is manufactured such that a terminal 233 and a die pad 235 that have a columnar shape are formed on a metal plate 231 by electroplating, the IC element 210 is mounted on the die pad 235, the IC element 210 is connected with the terminal 233 with the gold wire 213, a resin sealing is conducted, the metal plate 231 is peeled off from a resin molding part 236, and the resin molding part 236 is cut into individual products.
In detail, a resist is first applied on the metal plate 231 and an exposure and development treatment is performed on the plate so as to form a resist pattern 237 as shown in FIGS. 43A and 43B. Then, copper, for example, is applied by electroplating on a surface of the metal plate 231 exposed from under the resist pattern 237 so as to form the terminal 233 and the die pad 235 that have columnar shape as shown in FIG. 43C, and the resist pattern is removed as shown in FIG. 43D. The IC element 210 is mounted on the die pad 235 formed by electroplating and a wire-bonding is conducted as shown in FIG. 43E. The IC element 210, the gold wire 213, and the like are sealed by a resin as shown in FIG. 43F. The metal plate 231 is next peeled off from the resin molding part 236 as shown in FIG. 43G. Then the resin molding part 236 is cut into individual products so as to complete a package as shown in FIGS. 43H and 43I.
JP-A-2-240940, as a first example, discloses such technique that one surface of a supporting member of a planar lead frame is half-etched, an IC element is mounted on a die pad of the lead frame, wire-bonding and resin sealing are conducted, and another surface, which is not half-etched, of the supporting member is polished so as to remove the supporting member, completing the peripheral type package. JP-A-2004-281486, as a second example, discloses a technique for expanding the versatility of the area type package by radially arranging wires from the center of a substrate toward the outside in a planar view.
Peripheral type packages, area type packages, a package shown in FIGS. 43A through 43I, and a package disclosed in the first example in related art need a die pad or a substrate such as an interposer as an IC element mounting face. In addition, they need a specific lead frame, a specific substrate, or a specific photo-mask (for forming a column) depending on a size of the IC element and the number of external output (that is, the number of leads or balls). Especially, in terms of products in low-volume high-mix production, a lot of lead frames, substrates, or photo-masks are required for respective produce of the products, interfering the decrease of the manufacturing cost.
In the second example, the area type package corresponding to chips in various sizes is achieved by radially arranging wires from the center of the substrate toward the outside. However, in this technique, pad terminals of the IC element need to be arranged so as to surely overlap the wires that radially expand from the center of the substrate, in a planar view. Therefore, amount of freedom on designing a layout of the pad terminals decreases. Namely, the versatility of the package expands, while restrictions imposed on the IC element increase.